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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L Series
TMP93PW76
Preface
Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions.
**CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts (INT0, INT1), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fc or fs) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
TMP93PW76
CMOS 16-Bit Microcontroller TMP93PW76F 1. Outline and Feature
The TMP93PW76F is a system evaluation LSI having a built in One-Time PROM (128 Kbytes) for TMP93CW76/CU76/CT76F. A programming and verification for the internal PROM is achieved by using a general EPROM programmer with an adapter socket. The function of this device is exactly same as the TMP93CW76/CU76/CT76F by programming to the internal PROM and the TMP93PW76F is used as the evaluation chip of TMP93CW76/CU76/CT76F.
Product no.
TMP93PW76F
ROM
OTP 128 Kbytes
RAM
2.5 Kbytes
Package
P-QFP100-1420-0.65A
Adapter Socket no.
BM11146A
000707EBP1
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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DVCC DGND P73/SDA0 P74/SCL0 P75/AIN0/SDA1 P76/AIN1/SCL1 to AD P51/SO P52/SCK for P50 (SI) PWM0 PWM1 PA3/PWM2 8-BIT PWM (1CH) to PWM3 (VFT Driver) PD0 to 1/G8 to 9 PC0 to 7/G0 to 7 PC0 to 5/S8 to 13 PE0 to 7/S0 to 7 Vkk 8-Bit Timer (TC0) P96/TO1/TPG10 P52/INT2/TI1(TI0) P51/INT3/TI2 (TI4) P50/INT4/TI3 (TI5)/SI 8-Bit Timer (TC1) 8-Bit Timer (TC2) 8-Bit Timer (TC3) 8-Bit Timer (TC4) 8-Bit Timer (TC5) to SIO P93/TPG03 P97/TPG11 P91/TPG01/ VASWP P90/TP0/TPG00 P92/TP1 P94/CR P94/HA P87/COMP IN Head Amp SW Color Rotary (HA/CR) Timing Pulse Generater (TPG) RMTU, RMTD EXT CTL, CFG, DFG, DPG CFGTM Capture Input VISS/VASS CTL Duty Detector PCTL HS PV/PH for 8-BIT PWM PA0/PWM3/ PVPH (CAPIN) RMT-Input External-Input P82/RMTIN P83/EXT/TO Capture (Capture 0, 1, 2) VS V-Separation Port D Port C Port F Port E 14-BIT PWM (3CH) SIO I C bus I/F (IIC)
2 High frequency OSC (16 MHz)
A C E L IX IY IZ SP
X1 X2 PB0/XT1 PB1/XT2 TEST CLK
RESET
900/L CPU XW XB XD XH XI XI XI XS SR PC INT2, 3, 4 Others INT
W B D H
Real Time Counter (RTC) CPU INT
Low frequency OSC (32 MHz)
32 bits F
Interrupt Controller
P54/INT0 P53/INT1 TEST1 TEST2 TEST3 (NC)
RAM (2.5 KB)
ROM (128 KB)
Port 2 Port 1 Port 0
P20 to 27 P10 to17 P00 to 07
Watchdog Timer (WDT) Time Base Timer (TBC)
for P75 (AIN0) P76 (AIN1) 8 BIT AD Converter (10CH) ADREF
P40 to 47/AIN2 to 9
P75, 76/AIN0, 1 AGND
C-sync In
P86/CSYNCIN
P84/DPGIN P85/CFGIN P81/DFGIN P80/CTLIN
Figure 1.1 TMP93PW76F block diagram
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2.
Pin Assignment and Functions
The assignment of input and output pins for the TMP93PW76F, their names and functions are described below.
2.1
Pin Assignment
Figure 2.1.1 shows pin assignment of the TMP93PW76F.
TEST3 80 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 85 P02 P01 P00
95
90
P23 P24 P25 P26 P27 PE0/S0 PE1/S1 PE2/S2 PE3/S3 PE4/S4 PE5/S5 PE6/S6 PE7/S7 PF0/S8 PF1/S9 PF2/S10 PF3/S11 PF4/S12 PF5/S13 PC0/G0 PC1/G1 PC2/G2 PC3/G3 PC4/G4 PC5/G5 PC6/G6 PC7/G7 PD0/G8 PD1/G9 VKK
100
1
5 75
10 70
15 65
20 60
25 55
35
40
45
30
PWM0 PWM1 P90/TP0/TPG00
P95/HA P96/TO1/TPG10 P97/TPG11
P91/TPG01/VASWP P92/TP1 P93/TPG03 P94/CR
DVCC PA0/PWM3/PVPH PA3/PWM2
P83/EXT/TO1 P84/DPGIN P85/CFGIN
P80/CTLIN P81/DFGIN P82/RMTIN
Figure 2.1.1 Pin assignment (100-pin QFP)
P86/CSYNCIN
50
TEST2 TEST1 PB1/XT2 PB0/XT1 /RESET /TEST X2 X1 DGND CLK P54/INT0 P53/INT1 P52/INT2/TI1/TI0/SCK P51/INT3/TI2/TI4/SO P50/INT4/TI3/TI5/SI ADREF ADGND P47/AIN9 P46/AIN8 P45/AIN7 P44/AIN6 P43/AIN5 P42/AIN4 P41/AIN3 P40/AIN2 P76/AIN1/SCL1 P75/AIN0/SDA1 P74/SCL0 P73/SDA0 P87/COMPIN
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2.2
Pin Names and Functions
The names of input/output pins and their functions are described below. (1) MCU mode Table 2.2.1 Pin names and function (1/3) Pin name Number of pins
8 8 8 8 1
I/O
I/O I/O I/O Input Input I/O Input Input Input Input I/O Input Input Input Output I/O Input Input Input I/O I/O Input I/O Input I/O I/O I/O I/O I/O I/O Input I/O I/O Input I/O Input I/O Input port0: I/O ports port1: I/O ports port2: I/O ports
Functions
P00 to P07 P10 to P17 P20 to P27 P40 to P47 AIN2 to AIN9 P50 INT4 TI3 TI5 SI P51 INT3 TI2 TI4 SO P52 INT2 TI1 TI0 SCK P53 INT1 P54 INT0 P73 SDA0 P74 SCL0 P75 SDA1 AIN0 P76 SCL1 AIN1 P80 CTLIN P81 DFGIN
port4: Input ports Analog input: Input to AD converter Port50: I/O port (schmitt input) External Interrupt request input 4: Rising edge/Falling edge programable 16-bit timer3 (TC3) Input 3 16-bit timer5 (TC5) input 5 SIO received data Port51: I/O port (schmitt input) External Interrupt request input 3: Rising edge/Falling edge programable 16-bit timer2 (TC2): Input 2 16-bit timer4 (TC4): input 4 SIO sending data Port52: I/O port (schmitt input) External Interrupt request input 2: Rising edge/Falling edge programable 16-bit timer1 (TC1) Input 1 8-bit Timer0 (TC0) Input 0 SIO clock line Port53: I/O port (schmitt input) External Interrupt request pin1: Rising edge/Level programable Port54: I/O port (schmitt input) External Interrupt request pin0: Rising edge/Falling edge programable Port73: I/O port (schmitt input, Push-pull or open-drain output selectables) I2C bus SDA0 line Port74: I/O port (schmitt input, Push-pull or open-drain output selectable) I2C bus SCL0 line Port75: I/O port (schmitt input, Push-pull or open-drain output selectable) I2C bus SDA1 line Analog input 0: Analog input signal for AD converter Port76: Input port (schmitt input, Push-pull or open-drain output selectable) I2C bus SCL1 line Analog input 1: Analog input signal for AD converter Port80: I/O port (schmitt input) CTL Capture input (Capture 0) Port81: I/O port (schmitt input) DFG Capture input (Capture 1)
1
1
1
1
1 1 1
1
1 1
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Table 2.2.1 Pin names and function (2/3) Pin name
P82 RMTIN P83 EXT TO1 P84 DPGIN P85 CFGIN P86 CSYNCIN P87 COMPIN P90 TP0 TPG00 P91 VASWP TPG01 P92 TP1 P93 TPG03 P94 CR P95 HA P96 TO1 TPG10 P97 TPG11 PA0 PVPH PWM3 PA3 PWM2
Number of pins
1 1
I/O
I/O Input I/O Input Output I/O Input I/O Input I/O Input I/O Input I/O Output Output I/O Output Output I/O Output I/O Output I/O Output I/O Output I/O Output Output I/O Output I/O Output Output I/O Output
Functions
Port82: I/O port (schmitt input) Remote Control Signal Capture input Port83: I/O port (schmitt input) External Capture input (Capture 0) Timer Out 1 Port84: I/O port (schmitt input) DPG Capture input (Capture 0) Port85: I/O port (schmitt input) CFG Capture input (Capture 2) Port86: I/O port (schmitt input) C.sync Capture input Port87: I/O port (schmitt input) Envelope Comparate Input(to HA/CR) Port90: I/O port (Push-pull or open-drain output selectable) Timing Pulse output 0 TPG00: TPG0 output Port91: I/O port (Push-pull or open-drain output selectable) Video/Audio head switching control signal output TPG01: TPG0 output Port92: I/O port (Push-pull or open-drain output selectable) Timing Pulse output 1 Port93: I/O port (Push-pull or open-drain output selectable) TPG03: TPG0 output Port94: I/O port (Push-pull or open-drain output selectable) Color Rotary Output Port95: I/O port (Push-pull or open-drain output selectable) Head Amp Switching Control Output Port96: I/O port (Push-pull or open-drain output selectable) Timer Out 1 TPG10: TPG1 output Port97: I/O port (Push-pull or open-drain output selectable) TPG11: TPG1 output PortA0: I/O port PVPH 3-state Output PWM(8 bits) output 3 PortA3: I/O port(Push-pull or open-drain output selectable) PWM(14 bits) output 2
1 1 1 1 1
1
1 1 1 1 1
1 1
1
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Table 2.2.1 Pin names and function (3/3) Pin name
PWM0 PWM1 PB0 XT1 PB1 XT2 PC0 to PC7 G0 to G7 PD0,1 G8, 9 PE0 to PE7 S0 to S7 PF0 to PF5 S8 to S13 TEST1 TEST2 TEST3 CLK
Number of pins
1 1 1 1 8 2 8 6 1 1 1 1
I/O
Output Output I/O Input I/O Output Output Output Output Output I/O Output I/O Output Output Input Output Output
Functions
PWM(14 bits) output 0 (Push-pull or open-drain output selectable) PWM(14 bits) output 1 (Push-pull or open-drain output selectable) PortB0: I/O port (Open-drain Output) Low Frequency Oscillator connecting pin PortB1: I/O port (Open-drain Output) Low Frequency Oscillator connecting pin PortC: Output (High break down voltage outputs with pull-down resistor) Grid Drivers PortD: Output (High break down voltage outputs with pull-down resistor) Grid Driver PortE: I/O ports (High break down voltage outputs with pull-down resistor) Segment Driver PortF: I/O ports (High break down voltage outputs with pull-down resistor) Segment Driver TEST1 should be connected with TEST2 pin. TEST3 (NC) should be open connection. Clock output: Output (System Clock 2) clock. Pulled-up during reset. Can be set to output disable for reducing noise. (Initial Disable) Test pin: Always set to "Vcc" level Reset: Initializes LSI. (with pull-up resistor) High Frequency Oscillator connecting pins (16 MHz) High Frequency Oscillator connecting pins (16 MHz) VFT Driver power supply pin Power supply pin GND pin (0 V) Reference voltage input for AD converter GND pin for AD converter
TEST RESET
1 1 1 1 1 1 1 1 1
Input Input Input Output
X1 X2 VKK DVCC DGND ADREF ADGND
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(2) PROM mode Table 2.2.2 shows pin function of the TMP93PW76F in PROM mode. Table 2.2.2 Pin name and function of PROM mode Pin Function
A7 to A0 A15 to A8 A16 D7 to D0
CE OE PGM
Number of Pins
8 8 1 8 1 1 1 1 1 2
I/O
Input Input Input I/O Input Input Input Power supply Power supply Power supply
Function
Pin Name (MCU mode)
P27 to P20 P17 to P10 PA0 P07 to P00 P93 P91 P92
TEST
PROM address input PROM data input/output Chip enable Output control Program control 12.75 V/5 V (Program power supply voltage) 6.25 V/5 V 0V
VPP VCC VSS
VCC DGNG, ADGND
Pin Function
P90
RESET
Number of Pins
1 1 1 1 1 1 6 2
I/O
Input Input Input Output Input Output I/O Output/Input
Treatment of Pin
Fix to low level (security pin) Fix to low level (PROM mode) Open Self oscillation with resonator Fix to high level Short
CLK TEST3 X1 X2 P76, P75, P97 to P94 TEST1/TEST2 P47 to P40 P54 to P50 P74, P73 P87 to P80 PA3 PB1, PB0 PC7 to PC0 PD1, PD0 PE7 to PE0 PF5 to PF0 PWM0 PWM1 ADREF VKK
54
I/O
Open
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3.
Operation
This section describes the functions and basic operational blocks of the TMP93PW76F. The TMP93PW76F has PROM in place of the mask ROM which is included in the TMP93CW76. The other configuration and functions are the same as the TMP93CW76/CU76/CT76F. Regarding the function of the TMP93PW76F (not described), see the part of TMP93CW76/CU76/CT76F. The TMP93PW76F has two operational modes : MCU mode and PROM mode.
3.1
MCU Mode
(1) Mode-setting and function The MCU mode is set by opening the CLK pin (pin open). In the MCU mode, the operation is same as TMP93CW76/CU76/CT76F. (2) Memory-map The memory map of TMP93PW76F is same as that of TMP93CW76F. Figure 3.1.1 shows the memory map in MCU mode. Figure 3.1.2 show that in PROM mode.
000000H Internal I/O (144 bytes) Internal RAM (2.5 Kbytes) 000A90H Internal PROM (128 Kbytes) 000000H
000090H
1FFFFH
FE0000H Internal PROM (128 Kbytes-256 bytes) FFFF00H Interrupt vector table area (256 bytes)
(
I
Internal area)
FFFFFFH
Figure 3.1.1 Memory map in MCU mode
Figure 3.1.2 Memory map in PROM mode
ROM areas of TMP93CW76/CU76/CT76F are shown in Table 3.1.1. When TMP93PW76F is used as the evaluation-chip for TMP93CU76, the programmable area located address 00000H to 07FFFH should be full of data FFH. When TMP93PW76F is used as the evaluation-chip for TMP93CT76, the programmable area located address 00000H to 0DFFFH should be full of data FFH. Table 3.1.1 Memory of TMP93CW76/CU76/CT76 Product No.
TMP93CW76 TMP93CU76 TMP93CT76
ROM Area MCU Mode
FE0000H to FFFFFFH FE8000H to FFFFFFH FEE000H to FFFFFFH
PROM Mode
00000H to 1FFFFH 08000H to 1FFFFH 0E000H to 1FFFFH
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4.
4.1
Electrical Characteristics
Absolute Maximum Rating
Parameter
Power Supply Voltage Input Voltage Output Voltage (except PC, PD, PE, PF) Output Voltage (PC, PD, PE, PF) Output Current (except PC, PD, PE, PF) (per 1 pin) Output Current (PC, PD) (per 1 pin) Output Current (PE, PF) (per 1 pin) Output Current (per 1 pin) Output Current (total except PC, PD, PE, PF) Output Current (total of PC, PD, PE, PF) Output Current (total) Power Dissipation (Ta Soldering Temperature Storage Temperature Operating Temperrature 70C)
Symbol
Vcc VIN VOUT1 VOUT2 IOH1 IOH2 IOH3 IOL IOH1 IOH2 IOL PD Tsolder Tstg Topr
Rating
0.5 to 6.5 0.5 to Vcc 0.5 to Vcc Vcc 40 3.2 25 15 3.2 40 120 120 600 260 65 to 150 20 to 70 0.5 0.5
Unit
V
mA
mW C
Note:
The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
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4.2
DC Characteristics
Ta 20 to 70C
Parameter
Power Supply Voltage P0, P1, P2, P4, P9, PA, PB, PE, PF
RESET , P5, P7, P8 TEST
Symbol
Vcc VIL1 (CMOS) VIL2 (Schmitt) VIL3 (Fixed) VIL4 (Xtal) VIL1 (CMOS) VIH2 (Schmitt) Vcc fc fs
Condition
4 to 16 MHz 30 to 34 kHz
Min
4.5 2.7
Typ.
Max
5.5 0.3 Vcc
Unit
V
Input Low Voltage
0.3
0.25 Vcc 0.3 0.2 Vcc
X1 P0, P1, P2, P4, P9, PA, PB, PE, PF Input High Voltage
RESET , P5, P7, P8 TEST
2.7 to 5.5 V
0.7 Vcc
0.75 Vcc Vcc 0.3
Vcc
0.3
VIH3 (Fixed) VIH4 (Xtal) VOL VOH IOL 1.6 mA (Vcc 2.7 to 5.5 V) IOH (Vcc IOH (Vcc 400 A 2.7 to 5.5 V) 700 A 4.5 to 5.5 V)
X1 Output Low Voltage
0.8 Vcc 0.45 2.4 V 4.1 5 15 Vcc Vcc-0.2 2.0 50 80 0.02 0.05 5 10 6.0 150 200 10 1.0 30 Vcc 5 V 10% fc 16 MHz 18 15 5 50 30 25 6 0.2 50 28 25 8 80 45 40 15 10 A mA V k pF V mA V
Output High Voltage VOH1 PE, PF PC, PD Input Leakage Current Output Leakage Current Power Down Voltage
RESET
IOH ILI ILO VSTOP RRST CIO VTH
Vcc 4.5 V VOH 2.4 V 0.0 0.2 Vin Vin
A
VIL2 0.2 Vcc, VIH2 0.8 Vcc Vcc Vcc osc 5 V 10% 3 V 10% 1 MHz/100 mVp-p
Pull Up Resistor Pin Capacitance Schmitt Width RESET , P5, P7, P8 NORMAL RUN IDLE2 IDLE1 SLOW RUN IDLE2 IDLE1 STOP
Icc
Vcc 3 V 10% fs 32.768 kHz (typ: VCC Vcc 3.0 V)
2.7 to 5.5 V
Note 1: Typical value are for Ta
25C and Vcc
5 V unless otherwise noted.
Note 2: Icc measurement conditions (NORMAL, SLOW). Only CPU is operational; output pins are open and input pins are fixed.
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4.3
AD Conversion Characteristics
Ta 20 to 70C, Vcc 4.5 to 5.5 V
Parameter
Analog Reference Voltage Supply Analog Input Voltage Range Analog Current for ADREF Total tolerance (excludes quantization error) (Ta 25C, Vcc ADREF 5 V)
Symbol
ADREF ADGND VAIN IREF ET
Min
Vcc-1.5 Vss ADGND
Typ.
Vcc Vss 1.0
Max
Vcc Vss ADREF 1.5 3
Unit
V V V mA LSB
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4.4
Serial BUS Interface Timing
(1) I2C bus Logic Timing
Start Command tGSTA1 tODAT1 Stop Command tGSTP1 tGSTP3
SDA
tFSDA
tRSDA
tRSCL
tFSCL
SCL
tGSTA2
tSUODAT
tHDODAT
tHIGH
tLOW
tGSTP2
tCYSCL
Parameter
SCL cycle SCL low pulse width SCL High pulse width SDA Rising Time SDA Falling Time SCL Rising Time SCL Falling Time The time from start command write to start sheecense Start condition hold time, start generation of the first clock after this Delay time from SCL falling to data output Set up time of data output for SCL rising The time of holding data for SCL rising (Note 2) (Note 2) (Note 3) (Note 1) (Note 1) (Note 1) (Note 1)
Symbol
tCYCSCL tLOW tHIGH tRSDA tFSDA tRSCL tFSCL tGSTA1 tGSTA2 tODAT1 tSUODAT tHODAT tGSTP1 tGSTP2 tGSTP3
Min
2 /fc
N
Typ.
2
N-1
Max
Unit
s s s s s s s
/fc
2
N-1
/fc
2 /fc 2 0 4/fc 2 2 2
N-2 N-1 N-1 N-1
N
s s s s s
/fc 5/fc
The time from stop command write to starting stop sheecense The time from SDA falling to SCL rising (during stop sheecense) Stop condition set up time
/fc
s s s
/fc /fc
Note 1: The time of rising/falling depend on the feature of bus interface. Note 2: The worst case is at the first bit of slave address. Note 3: The worst case is at the acknowledge bit. Note 4: N: Diving value set by I2CCR1
SCK
000 001 010 011 100 101 110 111
N
6 7 8 9 10 11 12 reserved
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(2) Master SCL output timing The I2CCR1 are used to select a maximum transfer frequency directed from the SCL pin in the master mode. When rising time of the output clock (tRC) is at least 8/fc [s], a high-level time of the output clock (tHC) is tSCL. While the SCL line is fixed to low-level by a slave device,the output clock stops. The first clock (tHC [s]) after restart is (tSCL/2) (a) In case of tRC< (8/fc) [s]
1/FSCL [s] SCL pin (Output) FSCL fSCL
tHC
tSCL. (tSCL 1/fSCL [s])
tHC
tLC
tSCL/2 [s]
tLC
tHC 0.5VCC
tRC
(b) In case of tRC
(8/fc) [s]
1/FSCL [s]
tHC
tSCL [s], tLC
tHC 0.5VCC
tSCL/2 [s]
tLC
SCL pin (Output) FSCL fSCL/1.5
tRC
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(3) Clock Syncro 8 bit SIO mode a. SCK Input mode Parameter
SCK cycle SCK falling SCK raising Latch output data SCK raising SCK raising Latch input data Enable output data Enable input data
Symbol
tSCY2 tOHS2 tOSS2 tHSR2 tISS2
Expression Min
2X 6X tSCY2 6X 0 16X
5
Max
Unit
s s s ns ns
Note:
X
1/fc
b. SCK Output mode Parameter
SCK cycle SCK falling SCK raising Latch output data SCK raising SCK raising Latch input data Enable output data Enable input data
Symbol
tSCY2 tOHS2 tOSS2 tHSR2 tISS2
5
Expression Min
2X 2X tSCY2 2X 0 2X
Unit
s s s s ns
Max
2X
11
Note:
X
1/fc
tSCY2 SCK (Input Output mode) tOHS2 SO (Output data) tHSR2 SI (Input data)
tOSS2 tISS2
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4.5
Read operation in PROM mode
Ta 25 5 C Vcc 5V 10 %
DC/AC characteristics Parameter
VPP Read Voltage Input High Voltage (A0 to A16, CE , OE , PGM ) Input low Voltage (A0 to A16, CE , OE , PGM ) Address to Output Delay
Symbol
VPP VIH1 VIL1 tACC
Condition
Min
4.5 2.2 0.3
Max
5.5 VCC 0.3 0.8 2.25TCYC TCYC 200 ns
Unit
V V V ns
CL
50 pF
400 ns (10 MHz Clock)
A0 to A16
CE
OE
PGM
tACC
D0 to D7
Data Output
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4.6
Program operation in PROM mode
Ta 25 5 C Vcc 6.25 V 0.25 %
DC/AC characteristics Parameter
Programming Supply Voltage Input High Voltage (D0 to D7, A0 to A16, CE , OE , PGM ) Input low Voltage (D0 to D7, A0 to A16, CE , OE , PGM ) VCC Supply Current VPP Supply Current
PGM Program Pulse Width
Symbol
VPP VIH1 VIL1 ICC IPP PW
Condition
Min
12.50 2.2 0.3
Typ.
12.75
Max
13.00 VPP 1.0 0.8 50 50
Unit
V V V mA mA ms
fc 10 MHz VPP 13.00 V CL 50 pF 0.095 0.1
0.105
A0 to A16
CE
OE
D0 to D7
Unknown
Data-in stable
Data-out valid
tPW
PGM
VPP
Note 1: The power supply of Vpp (12.75 V) must be set power-on at the same time or the later time for a power supply of Vcc and must be clear power-on at the same time or early time for a power supply of Vcc. Note 2: The pulling up/down device on condition of Vpp 12.75 suffers a damage for the device.
Note 3: The maximum spec of Vpp pin is 14.0 V. Be carefull of a overshoot at the programming.
93PW76-21
2003-03-31

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